A clocked digital system has a regular clock rate or frequency for synchronous data handling. The system's maximum operating frequency is determined by the worst case delay in the system. The worst case delay depends on the synchronous switching of the digital logic in the system. The switching draws a lot of current from the power supply, such that, the system's local power supply voltage and ground voltage are bounced due to limited on-chip decoupling capacitance and non-zero power supply line resistance and inductance. This voltage bouncing results in insufficient current being provided for the system leading to an increased delay in state transition time for the logic, a lower clock rate and a decrease in system performance. As such, there is a need for a cost effective and efficient way to improve performance of a clocked digital system.